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holt integrated circuits www.holtic.com 1 HI-3718 3.3v arinc 717 / arinc 429 transceiver ds3718 rev. e 09/15 applications ? arinc 717 physical layer interface ? digital flight data acquisition units (dfdau) ? digital flight data recorders (dfdr) ? quick access recorders (cassette type) ? expandable flight data acquisition and recording systems pin configurations (top view) 32 - p i n p l a s t i c q u a d f l a t p a c k 7mm x 7mm body HI-3718pqi HI-3718pqt HI-3718pqm noconv - 1 rinb-40 - 2 rinb - 3 rina - 4 rina-40 - 5 hbp1out - 6 hbp0out - 7 bprz1out - 8 bprz0out - 9 hbpz - 10 slew1 - 11 gnd - 12 slew0 - 13 hbp1in - 14 bp1in - 15 bp0in - 16 24 - outha 23 - txoutha 22 - txouthb 21 - outhb 20 - outba 19 - txoutba 18 - txoutbb 17 - outbb 32 - vdd 31 - c1- 30 - c1+ 29 - v+ 28 - gnd 27 - c2+ 26 - c2- 25 - v- 32 - 31 - 30 - 29 - 28 - 27 - 26 - 25 - vdd c1- c1+ v+ gn d c2+ c2- v- noconv -1 -2 -3 -4 -5 -6 -7 -8 rinb-40 rinb rina rina-40 hbp1out hbp0out bprz1out 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - outha txoutha txouthb outhb outba txoutba txoutbb outbb bprz0out - 9 - 1 0 - 1 1 - 1 2 - 1 3 - 1 4 - 1 5 - 1 6 hbpz slew1 gn d slew 0 hbp1in bp1in bp0in HI-3718pci HI-3718pct HI-3718pcm 3 2 - p i n p l a s t i c qfn (7m m x 7m m) general description the HI-3718 is a low-power cmos transceiver designed to meet the requirements of the arinc 717 and arinc 429 specifcations. the device acts as an interface between arinc 717 or arinc 429 digital protocols and the harvard bi-phase (hbp) and/or bi-polar return-to- zero (bprz) encoded physical layers. the part includes a harvard bi-phase (hbp) or bi-polar return-to-zero (bprz) line receiver which produces correct hbp or bprz digital signals for input to a decoder. the device also has hbp and bprz line drivers capable of accepting hbp and bprz encoded digital signals. the device operates from a single +3.3v supply using only four external capacitors, making it the ideal interface device between an fpga and arinc 717 physical layer. the HI-3718 is available in very small 32-pin 7mm x 7mm chip-scale (qfn) and 32-pin quad flat pack (pqfp) plastic packages. features ? compliant with arinc 717-15 (june 6, 2011) and arinc 573 standards ? bprz line driver and line receiver are arinc 429 compliant ? operates from a single +3.3v supply with on- chip dc/dc converter ? independent harvard bi-phase and bipolar return-to-zero line drivers with digital slew rate control: set rise/fall times to 1.5s, 3.75 s, 7.5s or 10s ? line drivers have independent tri-state control ? hbp and bprz line receivers have common inputs ? dc/dc converter may be disabled if external v+ and v- supplies are desired. ? -40 inputs allow for do-160g level 3 lightning protection using only two external resistors. ? industrial and extended temperature ranges september 2015
holt integrated circuits 2 block diagram 40 k slew0 slew1 bp0in bp1in hbp0out bprz1out bprz0out hbpz hbp line driver 37.5 outba txoutba outbb rinb-40 rinb rina-40 rina 40 k dc/dc converter slew rate control 37.5 5 5 37.5 gnd txoutbb vdd outha txoutha outhb txouthb v+ noconv hbp1out v- c1 + cout c1- cfly+ c2+ c2- cfly- cout +3.3v v- v+ 37.5 5 5 hbp1in bprzline driver hbp line receiver bprz line receiver 10 f 0.1 f gnd csupply figure 1. HI-3718 block diagram HI-3718
holt integrated circuits 3 pin descriptions table 1. pin descriptions pin name function description internal pull-up / pull-down noconv input disables on-chip dc-dc voltage converter 50 k pull-down rinb-40 input alternate receiver negative input. requires external 40 k resistor rinb input receiver negative input. direct connection to arinc 717 bus (bi-polar return-to-zero or harvard bi-phase) rina input receiver positive input. direct connection to arinc 717 bus (bi-polar return-to-zero or harvard bi-phase) rina-40 input alternate receiver positive input. requires external 40 k resistor hbp1out output harvard bi-phase (hbp) line receiver high output hbp0out output harvard bi-phase (hbp) line receiver low output bprz1out output bi-polar return-to-zero (bprz) line receiver high output bprz0out output bi-polar return-to-zero (bprz) line receiver low output hbpz input setting this pin to a 1 tri-states the hbp line driver. 50 k pull-up slew1 input slew rate control pin. used with slew0 to set one of three programmable slew rates, 1.5 s, 3.75 s, 7.5 s or 10 s gnd power chip 0v supply (all gnd pins on package must be connected) slew0 input slew rate control pin. used with slew1 to set one of three programmable slew rates, 1.5 s, 3.75 s, 7.5 s or 10 s hpb1in input encoded hbp line driver input (high or low) bp1in input encoded bprz line driver high input 50 k pull-up bp0in input encoded bprz line driver low input 50 k pull-up outbb output alternate bprz line driver low output. requires external 32.5 resistor txoutbb output bprz line driver low output. direct connect to arinc 717 bus txoutba output bprz line driver high output. direct connect to arinc 717 bus outba output alternate bprz line driver high output. requires external 32.5 resistor HI-3718
holt integrated circuits 4 pin name function description internal pull-up / pull-down outhb output alternate hbp line driver low output. requires external 32.5 resistor txouthb output hbp line driver low output. direct connect to arinc 717 bus txoutha output hbp line driver high output. direct connect to arinc 717 bus outha output alternate hbp line driver high output. requires external 32.5 resistor v- converter dc/dc converter negative voltage c2- converter dc/dc converter fyback capacitor for v- c2+ converter dc/dc converter fyback capacitor for v- gnd converter dc/dc converter 0v supply (all gnd pins on package must be connected) v+ converter dc/dc converter positive voltage c1+ converter dc/dc converter fyback capacitor for v+ c1- converter dc/dc converter fyback capacitor for v+ v dd power chip +3.3v supply. decoupled with 0.1f, and 10f (10vdc). HI-3718
holt integrated circuits 5 functional description overview arinc 717 is a continuous transmission of 12-bit words in 4 second frames divided into four 1 second subframes. the data rate determines the number of words per subframe. arinc 717 requires a basic data rate of 64 words per second (wps) with support for 128, 256, 512 and 1024 wps. many arinc 717 controllers, including holts hi-3717, offer an expanded range of 32 to 8192 wps for testing purposes and future expansion. the frst 12-bit word of each subframe is reserved for a unique sync mark, an octal barker code which delineates the boundaries of the data frames. arinc 717 uses two encoding methods, harvard bi- phase (hbp) and bi-polar return-to-zero (bprz), which is similar to arinc 429. the HI-3718 transceiver allows direct connection to any arinc 717 compliant bus, allowing reception and transmission of either type of data. furthermore, the bprz channel may be used as an arinc 429 transceiver. arinc 717 line receivers the input data stream for arinc 717 can be one of two formats. the main arinc 717 bus to a digital flight data recorder (dfdr) uses harvard bi-phase (hbp) encoding and the auxiliary output bus to an aircraft integrated data system (aids) uses bi-polar return to zero (bprz) encoding, as shown in figure 2 . the HI-3718 line receivers are capable of connection to either hbp or bprz encoded busses via the rina/b or rina/b-40 pins. the bprz line receiver will also work with a standard arinc 429 bus. the line a and line b digitally encoded signals (hbp and bprz) will appear on the hbp[1:0]out and bprz[1:0]out pins respectively. note: if rina/b or rina/b-40 are connected to a hbp bus, the bprz[1:0]out pins may be left foating. similarly, if rina/b or rina/b-40 are connected to a bprz bus, the hpb[1:0]out pins may be left foating. the arinc 717 specifcation requires the following detection levels for the hbp inputs: state differential voltage hi +2 volts to +8 volts lo -2 volts to -8 volts the bprz input detection levels are the same as standard arinc 429 levels: state differential voltage hi +6.5 volts to +13 volts null +2.5 volts to -2.5 volts lo -6.5 volts to -13 volts the HI-3718 guarantees recognition of these levels with a common mode voltage with respect to gnd less than 25v for the worst case conditions (3.15v supply, 8v hbp signal level and 13v bprz signal level). design tolerances guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. if the signal (including nulls) is outside the differential voltage ranges, the HI-3718 receiver rejects the data. line receiver input pins the HI-3718 has an alternate set of line receiver input pins, rina/b-40, that are shared with the hbp and bprz line receivers. only one pair of pins, rina/b or rina/b-40, may be used to connect to the arinc 717 bus. the unused pair must be left foating. the rina/b-40 pins require an external 40 k resistor in series with each arinc 717 input. the resistors do not affect the arinc 717 receiver level detection thresholds. when using the rina/b-40 pins, each side of the arinc 717 bus must be connected through a 40 k series resistor in order for the chip to detect the correct arinc 717 levels. by keeping excessive voltage outside the device, the rina/b-40 input option is helpful in applications where lightning protection is required. please refer to the holt an-300 and an-301 application notes for additional information and recommendations on lightning protection of holt line drivers and line receivers. HI-3718
holt integrated circuits 6 dc/dc converter the HI-3718 requires only a single +3.3v power supply. the recommended decoupling capacitors for 3.3v vdd are ceramic 0.1f, and 10f, 10vdc minimum. an integrated inverting / non-inverting voltage doubler generates the rail voltages (5.7v) which then power the line drivers to produce the required +5v arinc 717 hbp and 5v arinc 717 bprz signal levels. the internal dual-polarity charge pump requires four external capacitors, two for each polarity generated by the charge pump. pins c1+ and c1- connect the external fy capacitor, cfly+, to the positive portion of the charge pump, resulting in 5.7v at the v+ pin that is generated by an on-board voltage converter. an output bulk storage capacitor, cout, is connected between v+ and gnd. the inverting negative portion of the converter works in a similar fashion, with cfly- and cout connected between c2+ / c2- and v- / gnd respectively. note that low esr capacitors must be used. recommended values and esr are given on page 10 . the noconv pin is set to 1 to disable the internal dc/dc converter. in this case, an external power supply should be used to supply +5v & -5v to the v+ & v- pins respectively. the fy capacitor pins may be left foating in this case. 0 msb 1 +5v hbp -5v +10v bprz -10v data lsb 1 0 0 0 0 0 1 1 1 1 1 figure 2. arinc 717 hbp & bprz differential bus signals arinc 717 line drivers the line drivers in the HI-3718 directly drive the arinc 717 hbp or bprz busses. the two arinc 717 hbp outputs (txoutha and txouthb) provide a differential voltage of 5v in accordance with the harvard bi-phase format. the two arinc 717 bprz outputs (txoutba and txoutbb) provide a differential voltage to produce a +10v one, a -10v zero, and a 0v null. the bprz line driver outputs are also arinc 429 compliant. the slew rate of the hbp and bprz outputs is controllable with pins slew[1:0] as shown in table 2 . a 3.75s slew rate conforms to all the required arinc 717 data rates. a 1.5 s data rate is provided for the higher data rates beyond the standard. in addition, slower slew rates of 7.5 s and 10 s are available to further optimize an application. table 2. line driver output slew rate control slew1 slew0 slew rate 0 0 7.5s 1 0 10s (same as arinc 429 low speed) 0 1 3.75s (arinc 717 data rates) 1 1 1.5s (higher data rates beyond arinc 717) no additional hardware is required to control the slope. HI-3718
holt integrated circuits 7 absolute maximum ratings supply voltages v dd ............................................... -0.3 v to +5.0 v v+ .............................................................. +7.0 v v- ............................................................. -7.0 v voltage at input pins rinxx ............... -120 v to + 120 v voltage at output pins txoutxx, outxx ......... v- to v+ voltage at all other pins ................. -0.3 v to v dd + 0.3 v dc current drain per digital input pin .................. 10ma solder temperature (refow) .......................... 260 o c junction temperature ................................... 175 o c storage temperature .................... -65 o c to +150 o c note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifcations is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions supply voltages v dd .............................................. +3.0 v to +3.6 v v+ .............................................................. +5.5 v v- ................................................................ -5.5 v operating temperature industrial screening ....................... -40 o c to +85 o c hi-temp screening ...................... -55 o c to +125 o c slope rate is set by on-chip resistors and capacitors. line driver input pins the hbp line driver is driven by a single input pin, hbp1in. this pin should be connected to a harvard bi-phase digitally encoded signal. the HI-3718 will automatically generate the compliment and output both the line a and line b hbp signal to drive the arinc 717 bus. the bprz line driver is driven by the bp1in and bp0in input pins. these pins should be connected to digitally encoded complimentary bipolar return to zero signals. the HI-3718 will output both the line a and line b bprz signals to drive the arinc 717 bus. forcing both the bp1in and bp0in input pins to a logic high will force the bprz line driver into a high impedance state. line driver output pins the harvard bi-phase (hbp) txoutha and txouthb pins as well as the bipolar return to zero (bprz) txoutba and txoutbb pins have 37.5 in series with each line driver output, and may be directly connected to an arinc 717 bus. the outha, outhb, outba and outbb pins have 5 of internal series resistance and require an external 32.5 resistor in series with each pin. outha, outhb, outba and outbb pins are for applications where external series resistance is applied, typically for lightning protection devices. please refer to the holt an-300 and an-301 application notes for additional information and recommendations on lightning protection of holt line drivers and line receivers. line driver tri-state capability each line driver has an independent tri-state function. forcing the hbpz pin high will force the hbp line driver into a high impedance state, independent of the bprz line driver. similarly, forcing both bp[1:0]in pins simultaneously high will force the bprz line driver into a high impedance state, independent of the hbp line driver. this independent functionality enables both line drivers to share a common bus if required in a given application. note: if the bprz and hbp line driver outputs are multiplexed into a single bus, care should be taken not to drive both inputs simultaneously. the user should adopt a break-before-make strategy, by forcing an active line driver into a high impedance state before the other is driven (see figure 7 ). HI-3718
holt integrated circuits 8 dc electrical characteristics v dd = +3.3v, t a = operating temperature range (unless otherwise stated) parameter symbol conditions min typ max unit line receiver inputs ? pins rina, rinb, rina-40 (with external 40 k ), rinb-40 (with external 40 k ) hbp differential input voltage (rina - rinb) hi v ihh common mode voltages less than 25v with respect to gnd 2.0 5.0 8.0 v lo v ilh -8.0 -5.0 -2.0 v hbp single-ended input voltage (ref. to gnd) rina hi v ihha 3.5 5.0 6.5 v lo v ilha -1.5 0 +1.5 v rinb hi v ihhb -1.5 0 +1.5 v lo v ilhb 3.5 5.0 6.5 v bprz differential input voltage (rina - rinb) one v ihb common mode voltages less than 25v with respect to gnd 6.5 10.0 13.0 v zero v ilb -13.0 -10.0 -6.5 v null v inul -2.5 0 +2.5 v bprz single-ended input voltage (ref. to gnd) rina one v ihha 3.25 5.0 6.5 v zero v ilha -6.5 -5.0 -3.25 v rinb one v ihhb -6.5 -5.0 -3.25 v zero v ilhb 3.25 5.0 6.5 v input resistance differential r i 140 k to gnd r g 140 k to v dd r h 100 k input current input sink i ih 200 a input source i il -450 a input capacitance (guaranteed but not tested) differential c i rina - rinb 20 pf to gnd c g 20 pf to v dd c h 20 pf logic inputs ? pins hbpz. slew1, slew0, noconv, hbp1in, bp1in, bp0in input voltage input voltage hi v ih 80% v dd v input voltage lo v il 20% v dd v input current input sink i ih 1.5 a input source i il -1.5 a harvard bi-phase (hbp) outputs ? pins txoutha, txouthb, (or outha, outhb with external 32.5 ) hbp differential output voltage (txoutha - txouthb or outha - outhb) hi v ohh no load 4.0 5.0 6.0 v lo v olh -6.0 -5.0 -4.0 v HI-3718
holt integrated circuits 9 parameter symbol conditions min typ max unit hbp single-ended output voltage (ref. to gnd) txoutha or outha hi v ohha no load 4.5 5.0 5.5 v lo v olha -0.5 0 +0.5 v txouthb or outhb hi v ohhb -0.5 0 +0.5 v lo v olhb 4.5 5.0 5.5 v hbp output tri-state current i ozh hbpz = v dd -5.75v < v out < +5.75v -1.0 0 +1.0 a bi-polar return to zero (bprz) outputs ? pins txoutba, txoutbb, (or outba, outbb with external 32.5 ) bprz differential output voltage (txoutba - txoutbb or outba - outbb) one v ohb no load 9.0 10.0 11.0 v zero v olb -11.0 -10.0 -9.0 v null v onul -0.5 0 +0.5 v bprz single-ended output voltage (ref. to gnd) txoutba or outba one v ohba no load 4.5 5.0 5.5 v zero v olba -5.5 -5.0 -4.5 v txoutbb or outbb one v ohbb -5.5 -5.0 -4.5 v zero v olbb 4.5 5.0 5.5 v bprz output tri-state current i ozb bp1in = bp0in = v dd -5.75v < v out < +5.75v -1.0 0 +1.0 a logic outputs ? pins hbp1out. hbp0out, bprz1out, bprz0out output voltage logic 1 v oh i oh = ?100 a 90% v dd v logic 0 v ol i ol = 1 ma 10% v dd v output current output sink i ol v out = 0.4 v 1.6 ma output source i oh v out = v dd ? 0.4 v -1.0 ma output capacitance c o 15 pf operating voltage range v dd 3.15 3.45 v operating supply current no load i dd 35 hbp max load i ddlh 600 differential output load 120 ma bprz max. load i ddlb 400 differential output load 120 ma line driver outputs shorted i ddsh see note 1 165 ma output impedance txout pins 37.5 out pins 5 note 1: txoutha and/or txouthb shorted to each other or ground. outha and/or outhb shorted to each other or ground (assumes external resistors are connected to outha and outha to comply with 37.5 ohm output resistance requirement). HI-3718
holt integrated circuits 10 note 2: txoutba and/or txoutbb shorted to each other or ground. outba and/or outbb shorted to each other or ground (assumes external resistors are connected to outba and outba to comply with 37.5 ohm output resistance requirement). converter characteristics v dd = +3.3v, t a = operating temperature range (unless otherwise stated) parameters symbol conditions min typ max units start-up transient (v+, v-) t start - - 10 ms operating switching frequency f sw - 500 - khz worst case maximum converter output v +(max) v dd = 3.6v. t = ?55 o c. open load. - - 6.0 v v ?(max) - - -6.0 capacitor requirements (see HI-3718 block diagram on page 2 for capacitor placement) v+ flyback capacitor, non-polarized x7r mlcc, 10v minimum c fly+ esr (cfly+) 500 khz 0.47 - - - - 500 f m v- flyback capacitor, non-polarized x7r mlcc, 10v minimum c fly? esr (cfly-) 500 khz 2.2 - - - - 500 f m two bulk storage capacitors, non- polarized x7r mlcc or tantalum, 10v minimum c out esr (cout) 500 khz 10 - - - 47 300 f m supply de-coupling capacitors, non- polarized x7r mlcc, 10v min. c supply two parallel capacitors - 10 0.1 - - 47 f f HI-3718
holt integrated circuits 11 ac electrical characteristics v dd = +3.3v, t a = operating temperature range (unless otherwise stated) parameter symbol conditions min typ max unit line driver propagation delay output high to low t phlx defned in figure 3 and figure 5 , no load 500 ns output low to high t plhx 500 ns line driver output transition times output high to low t fx pins slew[1:0] = 00 see figure 3 and figure 5 5.0 7.5 10.0 s output low to high t rx 5.0 7.5 10.0 s output high to low t fx pins slew[1:0] = 01 see figure 3 and figure 5 2.5 3.75 5.0 s output low to high t rx 2.5 3.75 5.0 s output high to low t fx pins slew[1:0] = 10 see figure 3 and figure 5 5.0 10.0 15.0 s output low to high t rx 5.0 10.0 15.0 s output high to low t fx pins slew[1:0] = 11 see figure 3 and figure 5 1.0 1.5 2.0 s output low to high t rx 1.0 1.5 2.0 s line receiver propagation delay output high to low t phlr defned in figure 4 and figure 6 , no load 500 ns output low to high t plhr 500 ns line receiver output transition times output high to low t fr 50 pf load 6.0 12.0 ns output low to high t rr 6.0 12.0 ns high impedance break-before-make on muxed line driver outputs t dz 1.0 s input capacitance (logic) 1 c in 10 pf output capacitance (tri-state) 1 c out bp1in = bp0in = v dd hbpz = v dd 10 pf note 1: guaranteed but not tested HI-3718
holt integrated circuits 12 +3.3v 0v +3.3v 0v +5v +5v +5v +10v +10v -10v -5v -5v -5v 90% 10% 10% 90% 0v 0v +3.3v 0v txoutba & outba v diff (txoutba - txoutbb & outba - outbb) txoutbb & outbb bp1in bp0in t plhx t plhx 50% 50% t phlx 90% 10% 50% 50% t phlx 90% 10% t fx t fx t rx t rx 0v 0v 0v figure 3. bprz line driver waveforms +3.3v 0v +3.3v 0v +10v -10v 50% 90% 90% 10% 10% 0v 0v +3.3v bprz1out bprz0out v diff (rina - rinb & rina-40 - rinb-40) t rr t fr 50% 50% 50% 50% 50% 50% 50% t plhr t phlr t plhr t phlr 0v 0v 0v figure 4. bprz line receiver waveforms HI-3718
holt integrated circuits 13 +5v -5v -5v 10% 90% 90% 10% t fx t rx 0v 0v +5v +5v +5v +5v 0v +5v 0v +5v 0v 0v +5v +3.3v 0v +3.3v +3.3v 0v txoutha & outha v diff (txoutha - txouthb & outha - outhb) txouthb & outhb hbp1in 50% 50% t phlx t plhx 10% figure 5. hbp line driver waveforms +5v -5v -5v +5v +5v 0v +3.3v 0v +3.3v +3.3v 0v v diff (rina - rinb & rina-40 - rinb-40) hbp1out 50% 50% t phlr t plhr hbp0out 90% 90% 10% 10% +3.3v +3.3v 0v 0v 0v 90% 90% 10% 10% t rr t fr t fr t rr 50% 50% 50% 50% t plhr t phlr figure 6. hbp line receiver waveforms HI-3718
holt integrated circuits 14 bp1in bp0in hi-z hbpz hpb1in hi-z active active active active active hi-z hi-z active t dz t dz figure 7. single-bus line driver outputs (multiplexed). HI-3718
holt integrated circuits 15 ordering information part number lead finish f pb-free, rohs compliant part number temperature range flow burn in i -40 o c to +85 o c i no t -55 o c to +125 o c t no m -55 o c to +125 o c m yes part number package description 3718pc 32 pin plastic 7mm x 7mm qfn - (32pcs7). lead fnish ? nipdau. 3718pq 32 pin plastic quad flat pack - (32pqs). lead fnish ? matte tin. hi - 3718px x x HI-3718
holt integrated circuits 16 revision history revision date description of change ds3718, rev. new 06/03/14 initial release rev. a 06/09/14 change transmit test conditions from 600 to no load. rev. b 08/04/14 update 32pcs7 package drawing (incorrect number of pins shown in drawing). rev. c 09/24/14 addition of 3.75s slew rate into features, pin descriptions table 1, arinc 717 line drivers description, and table 2 line driver output slew rate control. rev. d 10/03/14 add 3.75s slew rate information to line driver output transition times table. rev. e 09/03/15 remove max. power dissipation from absolute maximum ratings table HI-3718
holt integrated circuits 17 package dimensions 9.00 (0.354) bsc sq. 1.20 (0.047 ) 0.80 (0.031) 0.375 0.075 (0.015 0.003 ) 1.00 0.05 (0.039 0.002) 0.08 (0.003) 0.004 0.002 (0.10 0.05) 0 7 7.00 (0.276) bsc sq. see detail a detaila 0.20 (0.008) 0.60 0.150 (0.024 0.006 ) 0.145 0.055 (0.006 0.002) ma x r ma x bsc r mi n 32-pin plastic quad flat pack (pqfp) package type: 32pqs millimeters (inches) bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerence (jedec standard 95) 5.400 0.050 (0.213 0.002) 0.4000.050 (0.0160.002) 0.300 (0.012) 0.65 (0.026) 0.200 (0.008) 1.00 (0.039) 7.000 (0.276) bsc 5.400 0.050 (0.213 0.002) typ typ bottom v iew to pv iew bsc 7.000 (0.276) bsc ma x 32-pin plastic chip-scale package (qfn) package type: 32pcs7 millimeters (inches) electrically isolated heat sink pad on bottom of package. connect to any ground or power plane for optimum thermal dissipation. bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerence (jedec standard 95) HI-3718

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